This project attacks the high costs of architecting, implementation, and verifying computer systems as well as developing system and application software through the use of FPGA-Accelerate Simulation Technologies (FAST) simulators. Rather than having to develop a distinct set of simulation and evaluation tools for each task, FAST simulators have been demonstrated to be both accurate enough and sufficiently easy to write to be useful to architects and are both full-system and fast enough to be useful to software developers. Initial FAST prototypes were not, however, directly useful to computer system implementation and verfication. In addition, there is no mature methodology to verify FAST simulators themselves.
The specification of a FAST simulator, however, contains sufficient information to specify a set of implementations, thus begging the question of whether one or more implementations could be automatically generated from such a specification. This project is developing a tool chain to automatically transform a FAST simulator specification into an implementation, thus coupling architecture, implementation and software development, permitting all to be co-developed and making it easy for each to influence the other two. An implementation can also be verified using conventional methods, meaning such an automatic transformation provides a conventional method to verify FAST simulators.
