This award is funded under the American Recovery and Reinvestment Act of 2009 (Public Law III-5).
With pervasive usage of embedded systems in our daily life and infrastructures, strengthening the security of embedded system in its design and implementation has become a critical priority for the research community. This project targets augmenting the processor architecture for run-time secure processing. Since the architectural support can be made transparent to upper-level software, it cannot be easily circumvented by new software security attacks. Meanwhile, in-processor changes offer great efficiency. We are pursuing three research objectives to address random memory corruption caused by software attacks. First, we explore effective architectural augmentations of embedded processors to monitor code integrity, and incorporate the monitor in a realistic application-specific instruction set processors (ASIPs) design flow. Second, we utilize the embedded speculative architectures of processors as a cache for legitimate behaviors to validate program control flow, protecting control data and decision-making data. The program execution validations are sampled at critical points to reduce the performance degradation. Third, we scale architectural support in a single-core environment up to more sophisticated and increasingly popular multi-core platforms. A suite of CAD design tools will be released to public for free use. Our approach will lead to a real impact on modern secure embedded processor design. The project will also facilitate the integration of research and education across multiple disciplines, and the PI is especially keen on promoting participation of traditionally underrepresented minorities and women in such domains.
