Embedded digital systems are ubiquitous and may contain sensitive information that could be used for malicious purposes if fallen into the wrong hands. Therefore, strong cryptographic algorithms have been incorporated inside these devices. However, attackers have switched their targets from the cryptographic algorithms themselves to the hardware/software implementations of these algorithms, through ?side-channel? chip measurements. From a hardware perspective, such side-channel attacks can be implemented at both the circuit-level and architecture-level. Although much research has been performed in mitigating side-channel attacks, these solutions are inflexible, unsystematic, and have high overhead. The goal of this research is to develop a universal solution that synergistically combines both architecture-level and circuit-level countermeasures for mitigating all major categories of side-channel attacks, to yield an extremely secure, highly flexible, low overhead digital system design methodology. In this proof-of-concept project, preliminary research will be carried out at both levels. At the architecture-level, novel architectural support to mitigate architecture-level timing and access-driven attacks will be developed. At the circuit-level, Delay-Insensitive Ternary Logic will be utilized to design the new architectural support as well as other key components of a MIPS32 4K-compatible embedded microprocessor. The effectiveness and efficiency of side-channel attack resistance at both architecture-level and circuit-level will be evaluated. Educational modules of circuit-level and architecture-level attack mitigation will be developed. Graduate and undergraduate students, especially from underrepresented groups, will be involved in this project. The research outcome will be disseminated to the academic and industrial communities through journal articles, conference presentations, and appropriate websites.
