Proposal Title: CSR:Small:Collaborative Research: Combining Static Analysis and Dynamic Run-time Optimization for Parallel Discrete Event Simulation in Many-Core Environments Institution: SUNY at Binghamton Abstract Date: 07/06/09 This project investigates how a new processor paradigm (multi-core architectures) changes the way Parallel Discrete Event Simulation (PDES) is done. This topic is important given the wide use of simulation and the emergence of multi-core architectures. PDES is likely to play an increasingly important role in discrete event simulation as Moore?s Law is sharply curtailed and explicit parallelism becomes the major avenue for improving performance of sequential applications. Improving PDES performance translates to improved. Discrete Event Simulation (DES) is widely used for performance evaluation in many application domains. The fine grained nature of PDES causes its performance and scalability to be limited by communication latency. The emergence of multi-core architectures and their expected evolution into manycore systems offers potential relief to PDES and other fine grained parallel applications because the cost of communication within a chip is dramatically lower than conventional networked communication. Absent this dominant effect, PDES performance will be determined by issues such as load balancing, synchronization and optimism control, and the choice and configuration of various other algorithms and data structures of the simulator. Operation in a manycore environment introduces new system tradeoffs that must be effectively balanced by the system software. Primarily, the pressure on the memory system and resilience to load fluctuations will emerge as critical issues that we address in the proposed research. Finally, the more predictable nature of communication cost in this environment (due in part to the more frequent synchronization possible between nearby cores) can be exploited, especially by static analysis, for effective simulation. As multi-cores become the default microprocessor architecture, applications that are performance constrained must evolve to use parallelism to take advantage of the resources available on the cores. This project?s new PDES can have a significant impact on a number of applications that rely on discrete event simulations. The PIs plan to incorporate the research results into a graduate level course on parallel simulation techniques and to involve undergraduate students in the project.
