The project seeks to develop scalable synchronization mechanisms based on software transactional memory (or STM) for handling concurrency control in distributed, embedded, multiprocessor real-time systems. The project explores several competing abstractions for supporting STM (in such systems), investigate the relative merits of these approaches, and design and develop the protocols and algorithms necessary to support them. The project also seeks to identify the tradeoffs between semantic simplicity and efficient implementations of different STM systems, with particular emphasis on augmenting obstruction-free STM implementations with real-time contention managers. Among the algorithms that are being designed include real-time distributed commit protocols, distributed real-time cache coherence protocols, scheduling algorithms that can provide timeliness assurances given the retry behavior of STM, and efficient STM implementations. The project?s algorithms and protocols are being implemented and made publicly available in an open source form suitable for a real-time operating system or a real-time virtual machine. The project?s algorithms, protocols, analysis techniques, and implementations will allow distributed embedded real-time system programmers to use STM to simplify (distributed) concurrency control. Broader impacts of the project are sought through efforts to transition the project's results by collaboration with The MITRE Corporation and US Naval Surface Warfare Center, and increasing cultural interaction between students and faculty in the US and students and faculty in the Middle East and North Africa region, through graduate advising and teaching in the VT-MENA (Virginia Tech ? Middle East and North Africa) program.
Embedded systems are fundamentally concurrent: they sense concurrent physical processes and control their behavior by processing multiple streams of sensor input and control multiple actuators. They use concurrency control: computations process sensor data and control actuators by concurrently reading and writing shared memory data objects, while satisfying object consistency properties. They are real-time: sensor-to-actuator computations must satisfy application time constraints. Classical lock-based concurrency control has programmability, scalability, and composability challenges. These challenges are significant in emerging multicore architectures on which improved software performance must be achieved by exposing greater concurrency. Additionally, they are exacerbated in distributed systems due to the complexities of multi-node concurrency. Transactional memory (TM) is an alternative synchronization model that promises to alleviate these dif?culties with an optimistic concurrency control approach and a simple programming interface. TM is increasingly gaining traction with the growing availability of production hardware TM (e.g., Intel Haswell chip) and software TM (e.g., GCC compiler). At its core, the project’s research reveals that TM-based concurrency control is possible in embedded real-time software, and infact, has superior real-time schedulability advantages, in both multicore and distributed systems. The project’s real-time contention managers and distributed real-time concurrency control protocols enable real-time TM concurrency control in multicore and distributed systems, respectively. Their schedulability analyses have established upper bounds on transactional retries and (end-to-end) task response times. Analyses have also identified the conditions when the techniques achieve superior real-time schedulability than competitors in multicore systems (e.g., lock-free synchronization) and distributed systems (e.g., two-phase locking with priority inheritance). With TM, programmers also (naturally) enjoy TM’s better programmability and composability properties, especially in distributed systems, where lock-based concurrency control has poor programmability and composability. The project’s techniques have been implemented and rolled out as an experimental, open-source software system: the HyFlow distributed TM system, which is available at hyflow.org, and supports JVM languages (Java and Scala) and C++. Experimental studies using the HyFlow implementation have confirmed the analytical results, and have revealed real-time TM’s superiority in task response times over competitor techniques. The HyFlow TM system was transitioned to US Naval Surface Warfare Center Dahlgren Division’s Aegis Combat System software. Results from the research have been thoroughly disseminated to the relevant researcher and practitioner communities in different ways: rigorously peer-reviewed, relevant conference and journal publications; public release of the open-source, HyFlow TM software system; and additional documentation in non peer-reviewed technical reports. All are available at the project website (hyflow.org). The project also contributed to the development of the ECE/CS 5510 Multiprocessor Programming graduate course at Virginia Tech (cross-listed between ECE and CS departments), which is now routinely taught, and graduate education of several PhD and MS students. Additionally, the project has fostered greater research collaboration with VT-MENA/Egypt, through teaching of ECE/CS 5510 at Alexandria, Egypt, graduate education of VT-MENA PhD students, and transitioning of project alumni into faculty members and researchers in Egypt.
