Field Programmable Gate Arrays (FPGAs) are used in a variety of embedded applications in communication, space, automotive, medical devices and industrial control. Due to the safety-critical nature of many of these applications, the trustworthiness of the underlying hardware platform is imperative. FPGA-based embedded systems offer lower cost and reduced power consumption by aggressively embracing newer deep sub-micron technology process, which brings lifetime reliability concerns of the systems to the forefront. The impact of performance degradation is more significant in new technologies, resulting in accelerated aging and premature failures. Further, the reconfigurable nature of FPGAs and the heterogeneous components embedded in a FPGA make the reliability degradation and possible solutions to mitigate them different from those employed for application specific integrated circuits and microprocessors. Consequently, techniques to mitigate the impact of aging mechanisms are vital to ensure the trustworthiness of reconfigurable embedded systems, and are the focus of this research. The tools and techniques developed as part of this research will serve as a foundation for designing life-time aware reliable embedded systems and for catalyzing further research in this area. Due to the pervasiveness of embedded systems, providing solutions to improve lifetime reliability is anticipated to have a broad impact on the society. The project will involve both undergraduate and graduate students in all aspects of this research. The PIs will actively promote the projects to under-represented communities to improve student diversity. In addition, the PIs will integrate the research results in existing courses on VLSI design and reconfigurable systems.
Reliabile operations of embedded systems impact various aspects of our day to day life. This project has provided insight to different mechanisms that impact the reliability of embedded systems ranging from process variations that emerge from fabrication to life time degradation techniques. We have proposed several techniques to mitigate the adverse impact of effects such as soft errors, thermal variations, process variations and aging. Major contributions of this project include: (1) the first study on the impact of soft error vulnerability on multicore platforms running multi-threaded application (2) Design of configurable architectures inspired by algorithms used by the brain that are inherently robust to errors (3) thermal gradient aware clock skew scheduling techniques that boost performance in the presence of reliability challenges posed by temperature gradients (4) Adaptive error control schemes in on-chip communication fabrics that expend energy commensurate to the needs of the application. (5) Understanding the reliability concerns in using emerging device technologies such as memristors and tunnel FETs in designing systems. The project has contributed to training of several graduate students and has resulted in technical publications to disseminate the results to the broader community. The investigators have incorporated some of the results from this work into undergraduate and graduate curriculum as well as in tutorials and invited talks.
