As mobile embedded systems become more prevalent, there is an increasing demand to make processor pipelines more power efficient. Conventional pipeline inefficiencies include unnecessary accesses to the register file due to duplication or avoidable computation from constantly checking for forwarding and hazards at points where they cannot possibly occur, repeated calculation of invariant values, etc. It is desirable to develop an alternative processor design that can avoid these wasteful energy consumption aspects of a traditionally pipelined processor while still achieving comparable performance.
A statically pipelined processor is expected to achieve these goals by having the control during each cycle for each portion of the processor explicitly represented in each instruction. The pipelining is in effect statically determined by the compiler, which has several potential benefits, such as reducing energy consumption without degrading performance, supporting a less complex design with a lower production cost, and being able to apply more effective compiler optimizations due to instructions having more explicit control of the processor.
If successful, the broader impact of this research is manifold. The use of ultra-low power embedded devices, such as bio-implantable microelectronic devices, can significantly affect everyday activities. A new generation of ultra-low power processors will enable these devices to be more feasible to develop and deploy. Educational efforts to introduce the latest architecture and compiler enhancements in the classroom complement our research. Steps will also be taken to increase female and minority enrollment at both institutions in their Computer Science and Computer Engineering programs.
