The design processes used to convert algorithms to hardware implementations have obeyed the axiom that the specification and implementation need to be equivalent in a Boolean or numerical sense. However, algorithms from several interesting application domains exhibit the property of ?inherent resilience?, thereby offering entirely new avenues for performance and power optimization by relaxing the requirement of an exact equivalent implementation.
We explore scalable effort hardware design as an approach to tap the reservoir of inherent resilience and translate it into highly efficient hardware implementations. We identify mechanisms at each level of design abstraction (circuit, micro-architecture and algorithm) that can be used to vary the computational effort expended towards generation of the correct (exact) result, and expose them as control knobs in the implementation to achieve improved energy efficiency. Fully exploiting the potential of algorithmic resilience requires synergistic cross-layer optimization of scaling mechanisms at different levels of design abstraction. We investigate the nature of the tradeoffs that are possible through cross-layer optimization of scaling mechanisms, and develop techniques to determine the optimal operating point (in terms of the different scaling mechanisms) that maximizes performance or energy efficiency for any given level of output quality.
The proposed research will develop new design approaches that can enable unprecedented levels of performance and energy efficiency in hardware implementations of emerging applications such as recognition and mining. We will disseminate our results through publications, release of open source designs, integration into VLSI Design and System-on-Chip course material, and through Purdue?s nanoHub.
