A detailed architecture simulator is indispensable for computer architects. Unfortunately, today's fastest simulators do not provide desirable simulation throughput. The problem becomes even more serious when the target of a study is next-generation systems having hundreds of processor cores. The lack of a fast and versatile multicore system simulator will seriously hamper the productivity of researchers, as well as their capability to produce timely technical innovations. Moreover, existing teaching infrastructures are predominantly for outdated single-core systems. This project is for planning the submission of a CI proposal to create and deploy a very fast and versatile simulation and emulation infrastructure that can model and evaluate a large multicore processor system using realistic workloads. The proposed infrastructure focuses on the core components of architectural research in the multicore paradigm - the design of the memory hierarchy and interconnect. The PIs plan to integate developed high-speed trace-based software and FPGA-based simulation and emulation techniques that provide orders of magnitude speedup over conventional simulation techniques. The proposed novel dual-path approach is based on a common graphical interface that allows a user to easily and quickly specify an architecture configuration and test it using these trace-driven simulation techniques.
Modern computer processor architectures have become so complex that new ideas must be tested in simulation before being considered for inclusion in chips. The problem is even more serious when the architectures contain hundreds of processor cores. Unfortunately, today's fastest simulators do not provide desirable simulation throughput and are difficult to learn, use, and extend for new architectural techniques. Thus, the lack of a fast and versatile multicore system simulator seriously hampers the productivity of researchers, as well as their capability to produce timely technical innovations. Moreover, existing teaching infrastructures are predominantly for outdated single-core systems. In this work we developed Twin-CAM, a highly productive simulation and emulation environment that focuses on the core components of architectural research in the multicore paradigm---the design of the memory hierarchy and interconnect. Twin-CAM combines software and hardware acceleration techniques with a graphical front-end to allow for significant speedup in specification of the system as well as the simulation of the system. For the ``software path'', a cluster of machines is employed to execute the simulation. As part of this work, a graphics-processing-unit (GPU) acceleration was developed and integrated into the software flow. For the ``hardware path'', the design can be synthesized using the software resources and executed on an FPGA emulation board. In all cases, a repository of architecture configurations and multicore traces will be retained for use as input stimuli. As this was a planning grant to develop a community resource, to garner community consensus for the needs of the tool, we co-organized several workshops including an NSF workshop in Arlington, VA and a meeting at the MICRO conference to develop feedback for the needs of such a system. These workshops included participants from academia and industry with experience in developing community tools for advancing computer architecture research. The major outcomes of this research are the development and further integration of hardware and software artifacts with the potential to improve the productivity of computer architecture research. Additional outcomes include identifying a set of needs identified by the larger community beyond improved tools, including a repository mechanism for tools as well as experimental results and mechanisms for reproducibility of experiments. Based on the community feedback on the community needs, this work will be continued to develop a larger community infrastructure that addresses these larger problems for which Twin-CAM will be included as one of many vehicles.
