An Integrated Circuit (ICs) is at the core of many critical applications from financial and healthcare to avionics and military applications. Trustworthy ICs are therefore fundamental in ensuring the safety and security of our society. Unfortunately, cost considerations and globalization have pushed the IC design to a decentralized and distributed paradigm, where the design of a system-on-an-IC (SOC) spans various companies and countries with the fabrication of these SoCs taking place in third party (offshore) foundries. Threats, such as hardware Trojans, intellectual property piracy, and reverse engineering have emerged. This makes IC designers question their trust in the SOCs that they design. As SoCs are the roots of trust, applications that run on a compromised SOC platform is vulnerable regardless of how secure the underlying operating system and software is.
Complexity of ICs has been growing exponentially. To keep pace with this complexity, electronic system level (ESL) computer aided design (CAD) tools are being used to design ICs, resulting in simpler and automated design processes and shorter design cycles. This project develops a security-aware ESL design tool flow, and demonstrates the security vulnerabilities in industry standard ESL design flows by showing how one can reverse engineer an ESL generated design. This research develops approaches to build security into the ESL design flow, yielding reverse-engineering-resilient SoCs and systems.
