Computer networks are a foundational part of today?s digital society. A critical component of these networks is the infrastructure of base stations, access points, and routers that glues computers together, and moves network traffic (broken up into ?packets?) from place to place. Over time, in addition to packet forwarding, the network infrastructure has taken on many additional requirements to make it more efficient and robust, such as attack detection and prevention, access control, load balancing, packet scheduling, and measurement. To implement these requirements, new network devices have emerged that are ?programmable?. This proposal proposes to develop novel compiler technology to enable fast, efficient network programmability.
Programmable network devices (e.g., switches, SmartNICs, and FPGAs) are now rapidly becoming mainstream. While it is easy to get started with programming these devices, it is still hard to write fast packet-processing code that fits within the resource constraints of each device. Writing such fast packet-processing code today largely falls to experts with deep knowledge of the underlying hardware. While compilers should alleviate the burden of generating high-performance code, the compilers for these devices are still preliminary, and developing good compilers takes significant engineering effort and time. In response, the proposal proposes the use of program synthesis technology to build compilers that generate high-quality machine code for packet processing. This proposal has three key thrusts: (i) Code generation for programmable networks-developing code generators that generate high-quality machine code from a higher-level language (e.g., P4 or C) for a variety of different packet-processing substrates like programmable switches, FPGAs, and x86 processors. (ii) Speeding up program synthesis for code generation: Specializing program synthesis algorithms to the use case of code generation and speeding up synthesis algorithms in the process, so that code generation using program synthesis isn?t significantly slower than code generation using rule-based compiler techniques. (iii) Pushing the boundaries of synthesis-based code generation: Exploring relaxed notions of equivalence between higher-level programs and generated machine code so that higher-performance machine code can be generated at the cost of some loss of accuracy relative to the original program.
This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
