Computer Engineering (32) This is a proof of concept project that is educating students in the use of "double-loop learning" to improve their self-regulated learning (SRL) skills and thereby increase their learning capacity and their design skills. The study builds on earlier work funded by NSF that developed assessments of students' knowledge and skill in the design process. The specific objective of this project are: (1) to contribute to the understanding of how students learn to create open-ended designs and develop reflective practice, (2) to provide materials and an instructional model that can applied to other courses, and (3) to develop a validated instrument for measuring students' design process skill and reflective practice. The study has three phases. In the first phase the assessment instrument is being given to all students enrolled in electrical and computer engineering (ECE) to establish baseline performance levels both across the curriculum and in the computer engineering design courses. In the second phase, the junior-level computer engineering design course is being revised so that students use the process assessments as a basis for continuous improvement. After each third of the course, students will take the process assessments and use the results to devise improvement plans. The change in their understanding and use of appropriate design process, the quality of their design artifacts, and the impact on their reflective practice skills and attitudes is then being compared to that of students who took the course the previous year in the traditional format.
