Seniors in electrical engineering and microelectronics courses at San Jose State University are using Field Programmable Gate Array (FPGA) development systems as a design tool in their digital systems laboratory experience. New laboratory modules are used in teaching computer organization and digital system interfacing courses. The FPGA laboratory facilities also support senior student projects, providing a more interesting learning and teaching environment by enabling rapid prototyping and concurrent engineering.

Agency
National Science Foundation (NSF)
Institute
Division of Undergraduate Education (DUE)
Type
Standard Grant (Standard)
Application #
9250850
Program Officer
Daniel B. Hodge
Project Start
Project End
Budget Start
1992-09-01
Budget End
1995-02-28
Support Year
Fiscal Year
1992
Total Cost
$33,416
Indirect Cost
Name
San Jose State University Foundation
Department
Type
DUNS #
City
San Jose
State
CA
Country
United States
Zip Code
95112