With the potential for tens of millions of transistors enclosed within a package that grants only limited access to the internal circuitry, it is a challenge to determine whether a modern integrated circuit is fully functional. The Computer Engineering Department at the University of Minnesota, Duluth, is introducing a VLSI circuit design class in the Fall of 1993, and faces the task of testing the integrated circuits that students design. This project is adding a Logic Analysis System to an existing data acquisition lab to form a test station for functionally testing and characterizing digital integrated circuits. The existing data acquisition equipment, acquired through a prior NSF-ILI grant in 1988, is serving as the foundation for the test station, providing control functions and analog stimulus and measurement capabilities. The new equipment is adding the capability of exercising the device under test with a stream of test vectors and capturing its response at high speed. With NSF's help, this new equipment is enhancing the function of the existing NSF-supported data acquisition equipment to form a complete test station for testing and characterizing students' digital integrated circuit designs. The addition of this equipment is enabling development of a future course on techniques for testing and design for testability ideas.

Agency
National Science Foundation (NSF)
Institute
Division of Undergraduate Education (DUE)
Type
Standard Grant (Standard)
Application #
9350965
Program Officer
Daniel B. Hodge
Project Start
Project End
Budget Start
1993-04-15
Budget End
1995-09-30
Support Year
Fiscal Year
1993
Total Cost
$22,140
Indirect Cost
Name
University of Minnesota Twin Cities
Department
Type
DUNS #
City
Minneapolis
State
MN
Country
United States
Zip Code
55455