This project is improving the existing laboratory for the "Computer Systems" and "Computer Communication & Networks" courses at San Francisco State University by equipping the laboratory with new design and analysis tools. To reinforce the material learned in the classroom, undergraduates are using software and design tools based on advanced queueing models and digital circuit models to simulate the networks and computer systems that they design for their homework assignments and laboratory projects. Students are first learning the theoretical basis of computer systems, then designing various aspects of these components and systems, and finally testing their designs using computer simulations. In the newly structured courses, students are conducting actual simulations of their designs and are able to discover errors that are very difficult, if not impossible, to detect in a paper-and-pencil design. Students are uncovering their own mistakes in logic as they systematically check their own circuit designs and are increasing their understanding of the theoretical concepts used in their designs.
