This proposal will investigate novel approaches in the integration of high-K dielectrics and metal gates with vertical CMOS devices. This integration offers low temperature compatibility since high-K gatestack formation in vertical devices can be performed after the source/drain regions are defined, thus avoiding any high temperature exposure. This offers tremendous opportunity for achieving ultimate CMOS performance. Within the integration scheme, several novel approaches will be evaluated. Thin layers of metals placed on grown SiO2 layers will be used to convert SiO2 to a high-K layer. Chemical vapor deposition of low metal content SiO2 layers will be evaluated for their high dielectric constant, low leakage current, and excellent mobility. Metal gates will be integrated using CVD processing and workfunction modulation will also be explored. The integration knowledge obtained will be evaluated on a novel self-assembled device in which both channel length and channel thickness are lithography independent. In the education plan, several initiatives will be pursued such as: a) organization of a workshop on integration challenges of vertical devices, b) development of a new course (classroom and web-based) in EE at NCSU entitled "Beyond Bulk CMOS", c) development of a 30-min video tape on nano-chip technology, and d) development of a "nano-chip kit" that will include a microscope, Si wafer, discrete MOSFET, an integrated circuit chip, human hair and cross-sectional scanning and transmission electron micrographs of nanoscale feaures. The goal here is to excite young students (K-12) about nanotechnology by providing them with an early exposure to this fast growing field.
