This proposal is aimed at the integration of a high aspect-ratio, sub-100nm vertical airgap MEMS/NEMS technology with a 1um gate-length CMOS process, and the application of the resulting high aspect ratio CMOS-MEMS process to high-performance RF-sensory microsystems, as well as mixed-signal circuits. The implementation of the following two testbeds is proposed as technology demonstrators:
1. The high-performance sensor system testbed: Implementation of a novel CMOS-integrated inertial-grade (sub-ug resolution) acceleration/vibration sensor system with direct digital output. This single-chip sensor system will have 3-4 orders of magnitude higher sensitivity compared to the current state of the art integrated microsystem. It consists of a nano-precision lateral accelerometer and a high-performance mixed-signal interface circuit which utilizes 200um tall vertical poly-poly capacitors, yielding 2 orders of magnitude reduction in the die area.
2. The wireless RF components testbed: Implementation of MEMS-based high-Q on-chip frequency references "over a wide frequency range extending into GHz" integrated with CMOS electronics (MEMS-based VCO).
Over the past few decades, CMOS and CMOS-like processes have substantially grown in the number and thickness of the deposited layers on the surface of the Si substrate (the so-called back-end processes). However, the front-end processes have not grown proportionally and remained limited to the steps necessary to create the transistors. The out of silicon thickness of CMOS has grown to be almost an order of magnitude larger than the inside silicon thickness of it. The development of the integrated MEMS processes has followed the same model with integration of surface micromachined structures. The question is: can the front-end of the CMOS process be modified to bring new life to integrated MEMS by enhancing the performance and providing higher levels of functionality?
The intellectual merit of the proposed activity is to modify the front-end of the CMOS process using the deep reactive ion etching and refill technique to make use of the third dimension into the silicon and embed functionality (both electrical and mechanical) inside the CMOS-grade silicon substrate. The proposed process will allow the scaling of micromechanical structures into the nanometer domain through its unique ability to create sub-100nm vertical gaps and sub-micron silicon features. High aspect ratio poly and single crystal silicon structures (with high quality factors) separated by nanometer in size gaps will be integrated with CMOS circuits.
The broader impact resulting from the proposed activity is the ability to bring about significantly higher levels of performance and integration to the integrated MEMS and mixed-signal circuits. Higher performance levels and the ability to communicate wireless on a single silicon chip can open up the door to new opportunities and applications. Imagine having a tiny MEMS-CMOS silicon chip that can not only monitor very small changes in the environment, but also can transmit the monitored data real time in digital form to a receiver base, or communicate with a network of wireless sensory nodes. Such wireless sensory nodes can find numerous applications in various forms of environmental monitoring and energy-efficient systems.
