The proposed study seeks to monolithically integrate silicon nanoelectronics with spintronics. Vertical integration of double barrier magnetic tunnel junctions (MTJ) will be investigated with CMOS compatible silicon based quantum resonant tunnel diodes (RTD). It has been shown through physical models and simulations that a series combination of MTJ and RTD could increase the tunneling magnetoresistance (TMR) ratio significantly, which is desirable for ultra high-density memory applications. Utilizing ferromagnetic layers of different coercivities, the double barrier MTJ can have four distinct resistance values, representing four states in which the information is stored. The negative differential resistance (NDR) characteristic of the RTD is used to read the state of the MTJs, as well as to increases the TMR ratio without area penalty. The proposal will build upon the experience of the proposing team in successful integration of Si based Resonant Interband Tunnel Diodes (RITD) with CMOS. This device consists of Sage spacer layer sandwiched between two delta-doped regions of different polarities, all grown via low temperature molecular beam apiary. The basic double barrier magnetic tunnel junction structure will consist of Ta 5 nm/Ni79Fe21 3 nm/Cu 20 nm/Ni79Fe21 3 nm/Ir22Mn78 10 nm/Co75Fe25 4 nm/Al 0.8 nm-oxide/ Ni79Fe21 3 nm / Al 0.8 nm-oxide /Co75Fe25 4 nm/ /Ta 5 nm. A detailed research project will be undertaken to investigate processing constraints such as layout, clean processes, thermal budget and patterning process for the proposed integration. In addition, theoretical models will be developed to predict the response of the MTJ-RITD structures. This will be a collaborative effort between RIT, Naval Research Laboratory and Veeco located at Plainview, New York. RIT will carryout CMOS-RITD-MTJ chip design, mask fabrication, process development, fabrication, modeling and electrical test. NRL will provide MBE growth for RITD structures and Veeco will provide MTJ films depositions.

Intellectual Merit The novelty of this proposed research lies in the fact that it consists of a heterogeneous set of novel and widely spread disparate technologies integrated on silicon CMOS compatible platform that has a potential to develop into new architectures for logic-memory applications. In addition, the proposed technology utilizes three different state variables in the novel information processing: electric charge, spin orientation, and quantum state. By the convergence of these functionalities, the MTJ/RITD MRAM technology is expected to outperform the current state-of-the-art 1T-1MTJ MRAM architecture in term of cell size due to the vertical integration approach, high signal-to-noise ratio due to MR ratio enhancement, and ease of fabrication and cost. The coexistence of magnetoelectronics with conventional electronics will open new frontiers. The PI, and Co-PI have extensive experience in RITD fabrication with CMOS chips and synergistic collaborations with NRL and Veeco.

Broader Impact The intersection of nanotechnology and electronics will yield many new innovations over the coming decades. It is anticipated that convergence of various technologies with the standard silicon technology has the potential for tremendous impact in memories and displays and subsequently in logic. The proposed research is aimed at the development of electronic.spintronic systems such as multi-value memory that will provide ultra high density memory, extremely important for the information demands of the future and for maintaining innovative edge of the US industry in the era of global competition. The study will involve participation of faculty and students with a national laboratory (NRL) and industry (Veeco). The PI and Co-PI will develop new courses- "Fundamentals of Spintronics" and "Novel Memory Technologies" that will enrich engineering education. These courses will also be made available for distance delivery for industry and academia. The program will promote science and engineering in the community through K-12 partnerships and in attracting community college and underrepresented student groups to science and engineering.

Agency
National Science Foundation (NSF)
Institute
Division of Electrical, Communications and Cyber Systems (ECCS)
Application #
0501460
Program Officer
Pradeep P. Fulay
Project Start
Project End
Budget Start
2005-05-01
Budget End
2009-04-30
Support Year
Fiscal Year
2005
Total Cost
$261,814
Indirect Cost
Name
Rochester Institute of Tech
Department
Type
DUNS #
City
Rochester
State
NY
Country
United States
Zip Code
14623