Advances in VLSI technology will soon allow a single chip to contain more than one billion transistors, indicating that a large number of complex processing units (such as CPU, DSP, multimedia processor) shall be integrated into one packaged chip. In these new systems, communication resources are competed by the vast volume of computing resources. Following a communication-centric design style, Network-on-Chip (NoC) was proposed to mitigate the complex communication requirements for these densely integrated chips. In this proposal, we investigate a novel energy-efficient and highly scalable NoC architecture to address the following important problems: scalability, energy efficiency and reconfigurability. In detail, we will (i) design and analyze a customizable Recursive Diagonal Torus (RDT) architecture for NoC, (ii) investigate the effects of various reconfigurable components on the performance of the proposed NoC architecture in terms of scalability and routing performance, (iii) investigate the energy-efficient communication protocols pertaining to the proposed NoC architecture, and (iv) develop a generic simulation framework to evaluate the proposed NoC architecture and related switching, routing, and reconfiguration schemes.
The intellectual merits of the proposed research include: (i) applying the RDT structure, a novel parallel architecture, to the design of NoC, (ii) developing a generic simulation framework that will benefit the research communities pursuing research in this emerging area, and (iii) investigating the generic reconfigurable NoC architecture that will help understanding of the fundamental issues related to the NoC paradigm.
The broader impacts of the proposed research include improving existing courses as well as developing new ones to enhance our electrical and computer engineering curriculum, and involving undergraduates in the proposed research work.
