An orthogonal four-wire signaling technique based on Code Division Multiple Access (CDMA) principles will be developed for chip-to-chip electrical communications. The technique achieves 50% more aggregate data bandwidth per wire than conventional differential signaling. It can be generalized to higher wire (and pin) utilization and better electromagnetic crosstalk suppression, enabling future multi-terabytes/second links. An 18 Gb/s prototype chip-to-chip interface over four 6" FR4 traces will be built in a digital CMOS process as a proof of concept. The proposed budget has been revised to support two graduate students instead of one; PI summer support and prototype fabrication and testing costs have been reduced. The revision does not alter the technical scope of the project; but the prototype would be built in 130nm (instead of 90nm) CMOS to offset fabrication costs.
The intellectual merit of the research is that it presents a different approach to improving chip-to-chip communications. It recognizes that a bundle of distinct wires, package pins, routing vias etc. is a shared medium at Gb/s data rates owing to inevitable electromagnetic crosstalk and component errors, allowing the application of well established communication theoretic principles such as CDMA to increase the aggregate data bandwidth and suppress crosstalk.
The broader impacts of the project are two fold: first, it addresses the chip-to-chip communication bottleneck, crucial to the growth of the electronics industry; second, it will better prepare future engineers by training them in the fundamental interplay between circuit design, signal processing, and communication theory.
