The objective of this research is to explore the response of system-in-a-package to electrical overstress events, and to develop the know-how to protect against these without compromising the system performance. The approach is to design an electrostatic discharge protection network for the system, and then use circuit simulation to study its response to various electrical stresses. Electrical overstress events are full-system phenomena, yet the circuit to be simulated must be of limited size. The researchers will identify the typical failure spots in system-in-a-package and construct circuits that produce the correct response at these locales. Models of the various elements in the circuit will be constructed based on the results of electrical measurements and 3-dimensional electromagnetic simulation. Measurements are made using short duration, high amplitude pulses that emulate electrostatic discharges.
Broader Impact Electrostatic discharge / electrical overstress is responsible for more than half of integrated circuit failures. The implications of using vertical stacking to integrate multiple die in one package are not known, nor is known the impact of integrating die that were fabricated in disparate technologies. In a system-on-a-chip, the common silicon substrate provides a favorable path for dissipation of static charge; for system-in-a-package, this low impedance path is absent. This research will identify reliability hazards unique to system-in-a-package and provide solutions. The research team will offer an intensive, engineering outreach program to 4th and 5th grade children at a Title I school. The outreach modules tie into the research program. A workshop on microelectronics will be provided for elementary school teachers, and for the undergraduate Engineering Advocates.
