The objective of this research is to investigate and develop III-V compound semiconductor based devices integrated on a manufacturable silicon platform. AmberWave Systems has developed a novel selective epitaxy technique known as Aspect Ratio Trapping that involves selective deposition of compound semiconductors on high aspect ratio trenches in silicon. In this project, basic devices will be fabricated and characterized followed by realizing III-V resonant tunnel devices with silicon circuitry. Intellectual merit: The ability to form a wide variety of heterostructures on silicon is critical for enhancing the performance of integrated circuits for future information technology revolution as scaling of silicon devices is approaching fundamental limits. This proposal encompasses a strategic and synergistic partnership between a small innovation company, AmberWave Systems, engaged in cutting edge advanced semiconductor substrate engineering and RIT that has a highly recognized microelectronic engineering program with a student run integrated circuit laboratory. This proposal will facilitate this partnership in achieving critically needed breakthroughs.
Broader Impact: The technology developed under this proposal will have far reaching implications in new areas of high frequency mixed signal, optoelectronic, photonic system on chip technologies as well as in extending silicon beyond the perceived technology roadmap. The students will be exposed to an R&D environment and experience technology development while learning advanced techniques. The company will get access to an established integrated circuit fab where a significant amount of R&D work can be performed involving faculty and students. The outreach activities will be targeted at involvement of high school teachers and attracting minority and inner city students.
The goal of this Industry-University Collaborative GOALI proposal between AmberWave Systems (AWS) and Rochester Institute of Technology was to investigate and develop III-V compound semiconductor (CS) based devices fabricated via a novel innovative technique integrated on a manufacturable Si platform. CS devices, due to their superiority in high frequency, mixed signal applications make their way into consumer and special niche applications, innovative approaches that develop a viable process for the fine-scale heterogeneous integration of CS with standard Si CMOS will be needed. This project focused in particular on the integration of III-V based tunneling devices on a Si platform. The key technology to realize these devices was known as aspect ratio trapping, which was developed at Amberwave Systems. Intellectual Merit: This collaborative project resulted in several key demonstrations throughout the life of the project. First, the PIs demonstrated Ge tunnel diodes fabricated on Si with comparable performance to control Si devices. These diodes utilized a technique known as alloying to realize the abrupt tunnel junction. Second, the ambitious goal of demonstrating a GaAs/InGaAs tunnel diode on a Si substrate. This device, which was presented as a seminal paper at the 2008 IEEE IEDM conference, had a record peak-to-valley current ratio (PVCR) of 56. The significance of this result is that it was one of the highest reported PVCRs for any tunnel diodes in 40 years of research, a clear indicator of the excellent material quality. This also opens the door for research into III-V tunneling field effect transistors (TFET). The TFET is widely considered to be one of the next generation transistors. Following the strong advice of a number of collaborators, the emphasis of this work shifted toward demonstrating ultra-high current density tunneling devices as well as the scaling properties of tunneling diodes. Both of these goals were demonstrated by the PIs. The scaling studies were initiated on the III-V on Si Esaki diodes reported at the IEDM. These devices were demonstrated to work for radii conservatively reported down to 50 nm, and possibly as small as 8 nm. In general the device performance improved with reduced geometries. The technique developed was then used to test InGaAs Esaki diodes. The resulting current density was found to be 1 MA/cm2, the highest current density ever reported in a tunnel diode. This result was again quite significant for TFETs as it demonstrated the feasibility of ultra-high current density TFETs. Broader Impact: Our outreach efforts were coordinated in conjunction with Mr. Daniel Fullerton, a physics teacher at West Irondequoit High School (Irondequoit, NY). Mr. Fullerton was the identified teacher because of his unique experience working in the semiconductor industry prior to teaching, and we felt that it was best to distribute his involvement throughout the year. Our outreach program was developed to target AP physics students throughout Monroe County in their last month of school. In this month, there is freedom to deliver course content such as a limited device physics module. Mr. Fullerton has been in touch with various physics teachers across Monroe County. This program was prototyped in 2010 and repeated in 2011 with great success. Furthermore, this project has resulted in the training of several domestic graduate students (Mr. David Pawlik-pursuing a PhD, Mr. Paul Thomas- pursuing a PhD, Mr. Michael Barth-MS received on project-pursuing a PhD at Penn State University). Several research experience for undergraduates were also involved in the project (Michael Barth, Kelly Johnson, Brian Romancyzk, Eugene Freeman, Marie Rohrbaugh, and Ken Nagamatsu). Three of these students are presently pursuing PhD degrees outside of RIT. A fourth (Romanczyk) is planning to attend graduate school and is in his senior year. A fifth student (Johnson) is presently employed by the National Security Agency (NSA). The remaining student (Rohrbaugh) is in her third year of schooling and determining future directions.
