The objective of this research is to develop a novel design engineering technique for parallel fabrication of controllable, scalable, and reproducible single electron transistor (SET) devices using carbon nanotubes (CNTs). The approach is to fabricate SET through (i) control positioning of individual CNT between source and drain electrodes via AC dielectrophoresis, (ii) engineering tunnel barrier formation by bending the CNT with a raised local aluminum oxide gate thereby forming a quantum dot, and (iii) controlling the size and operation of the dot by the same local gate. Intellectual Merit: Controlled fabrication and assembly of SET with different sizes from 100 nm to 20 nm will be demonstrated by integrating top down and bottom up techniques. Electronic transport properties will be studied. Room temperature operation and a novel ultra sensitive quantum sensor will be demonstrated. In contrast to the existing SET fabrication techniques, the proposed approach offers parallel fabrication of reproducible SET devices using one dimensional nanostructures. Broader Impact: The proposed research will have significant impact on nanoelectronics, information processing, and ultra sensitive chemical and biological sensing. Continued miniaturization of Si-Metal Oxide Semiconductor Field Effect Transistor will soon hit a major bottleneck. SET will become crucial for information and signal processing. For educational development and outreach, the PI proposes (i) development of a new graduate course titled, Nanoscale Physics and Nanoelectronics, (ii) modification of an undergraduate Nanophysics course, (iii) research training of minority and female students, high school students and teachers and (iv) community outreach through lectures, web based dossier and news letters.
In this NSF funded research, we made significant advance in parallel fabrication of scalable, controllable and reproducible single electron transistor devices using a novel design engineering approach. If the current trend of miniaturization of Si-Metal Oxide Semiconductor Field Effect Transistor (Si-MOSFET) has to continue, the device size will hit sub-5 nm scale in a decade or so. Not only that the fabrication of sub-5 nm device by current top down technology will be extremely challenging but also the operation of such a device will NOT be based on diffusive transport. This is due to the fact that as the device size becomes smaller, the self capacitance C (proportional to the dimension) of the device also becomes smaller. Therefore, there is a finite energy cost of e2/C for placing an additional electron into the device. This energy is inversely proportional to the size of the device and can become significant in nanoscale devices compared to the thermal energy. Consequently such a device will operate quantum mechanically via single electron tunneling. A device in which single electron tunneling can be controlled one electron at a time by applying voltage to a nearby gate is called single electron transistor (SET). SETs are very important for fabricating low powered and high frequency quantum devices. However, for the practical realization of SET based electronic devices, several key challenges need to be addressed: (i) controllable, scalable and reproducible SET need to be fabricated, (ii) operation at room temperature need to be demonstrated, and (iii) simultaneous placement of the individual SETs on exact substrate location over large area must also be demonstrated. In order to address these challenges novel fabrication techniques are required that would enable parallel fabrication of SETs with controllable and reproducible sizes, tunnel barriers and gates. In this project, we developed a simple device engineering approach for the controlled fabrication of a single electron transistor (SET) using single walled carbon nanotube (SWNT) by employing aluminum/aluminum oxide local gate as a mechanical template. The local gate electrode (i) acts as a "mechanical template" to bend the nanotube at its edges to introduce tunnel barriers, (ii) its width defines the size of the quantum dot, and (iii) it controls the operation of the SET device. We investigated the physics of tunnel barrier formation by performing detailed low temperature transport spectroscopy measurements of the mechanically templated SWNT QDs to determined how the tunnel barriers evolve with both back gate and local gate voltage. Using dielectrophoresis, we also developed technique for the parallel fabrication of CNT SET. By reducing the size of the "template" we were able to fabricate the room temperature SET. In our educational activity, seven graduate students, three undergraduate students, two postdoctoral scholars and two high school students received training. Participants received training on the state of the art micro/nano device fabrication, electrical and optical characterizations, report and paper writing and presentation skills. One Ph.D., one MS and one undergraduate thesis was resulted from this project. Another Ph.D. thesis will be submitted by summer 2014. Among the participants, one graduate and one undergraduate were female fulfilling NSF’s requirement of broadening participation in STEM education. The project contributed 26 published peer reviewed papers and the students were coauthor of these papers. The research done through this project has been integrated to graduate teaching by developing new course such as Physics of NanoElectronic Devices. Outreach to K-16 students were done by hosting lab demonstration to students of UCF Summer Research Academy, lab visits of Florida Lt. governor and orange county mayor, demonstration at local libraries through "NanoFest", and publishing news letters.
