Fabrication of the NEM and NEMFET Logic Gates via Top-Down and Bottom-up Processes
H.-S. Philip Wong hspwong@stanford.edu Stanford University
250 Word Abstract:
The objective of this research is to demonstrate for the first-time ultra-low power logic gates based on nanoelectromechanical (NEM) switches and NEM field-effect transistors. The proposed devices will solve the ever aggravating leakage and static power consumption problem of the CMOS technologies. The approach is to pursue simultaneously the lithography-based top-down processes and the nanowire/carbon nanotube-based bottom-up techniques. The proposed research aligns well with the EPDT program which aims at improving the fundamental understanding of devices and components based on the principles of electronics and electromechanics. The intellectual merit resides in the experimental realization of extremely low power ULSI logic systems combining two traditionally distinct domains (MEMS and CMOS logic). Micron-sized MEMS devices will be extended into the nanoscale regime. The ultra-low power operation of the proposed devices follows from the fact that the signal propagation is based not only on the movement of charge but also on the displacement of a solid rod. This distinguishes the NEM relays and the NEMS-based transistors from the conventional MOSFETs. The broader impacts will advance diversity in the nanoelectronics workforce and provide intellectual technology transfer, integration of research and education, public education, minority student outreach, and promotion of partnerships. Specifically, collaboration with the producers of the award-winning Silicon Run Film Series will result in new educational films on MEMS and nanoelectronics. They will serve as a resource to educators teaching in these new fields and assist with the professional development of instructors in supporting disciplines.
Three terminal nanoelectromechanical (NEM) relays operate similarly to CMOS transistors, with the current flow between the source and the drain terminals controlled by gate biasing. However, they differ in that they have: 1) zero off-state leakage, with all three terminals separated by an air gap in the off-state, 2) sharp on/off transition, determined by the making and breaking of the contact between the source and the drain, and 3) hysteresis, with the turn-on voltage (pull-in voltage, Vpi) being larger than the turn-off voltage (pull-out voltage, Vpo). With standby power of CMOS circuits already optimized to be comparable to the active power with device scaling, the first two properties make NEM relays attractive devices for low standby power applications. However, the replacement of all CMOS transistors with NEM relays is problematic, because the turn-on speed of relays is limited by the mechanical movement of the beam. The switching speed of fabricated relays have been measured to be on the order of 100 ns, whereas that of scaled NEM relays is projected to be on the order of 1 ns. This is still at least 103 times slower than current CMOS devices. Therefore, applications have been proposed, where a combination of NEM relays and CMOS is used to capitalize on the benefits of each. These include power gating using MEMS switches (50% battery life increase expected), CMOS-NEM field-programmable-gate-array (FPGA) (37% leakage power and 28% critical path delay reduction expected), and CMOS-NEM static random-access memory (SRAM) (85% static power, 60% write delay, and 10% read delay reduction expected). Laterally actuated Pt relays are fabricated using e-beam lithography on top of CMOS fabricated at the NSF funded National Nanotechnology Infrastructure Network (NNIN) node of the Stanford Nanofabrication Facility. The fabricated relay is shown to operate as projected and demonstrated the feasibility of integrating NEM relay onto CMOS. As relays continue to scale to sub-1 V actuation voltages with gap sizes on the order of 10 nm, conventional CMOS with 1 V power supply can be used. Two NEW devices have been invented during the course of this project. They are particularly promising as they pave the way for NEW applications beyond what has been envisioned for NEM relay technology so far. Nanoelectromechanical Memory NEM relays are promising for nonvolatile (NV) memory applications due to their inherent electromechanical hysteresis. The Nanoelectromechanical Memory (nRAM) is a simple two-terminal NEM switch where the stored logic states are represented by the beam position ("0" = beam up, "1" = beam down). The most significant feature of the nRAM is the sharpness of the hysteretic transitions, enabling to implement a crossbar array without using cell selection devices. This improves the device density considerably and makes the 3-D integration possible, since no transistor or diode is required. Analog Nanoelectromechanical Relay with Tunable Transconductance NEM relays naturally fit to the requirements of logic and memory devices due to its features including zero leakage, infinitely sharp on/off transitions, and a square hysteresis window. However, analog signal processing with the NEM relays is not feasible since the drain current amplitude cannot be controlled by the gate voltage. We show by simulation that a three-terminal NEM relay combined with a feedback resistor provides a tunable transconductance Gm over an adjustable input-voltage range. An analog NEM transistor (NEMT) consists of a NEM relay in series with a feedback resistor Rf . The whole structure is perceived as a single 3-T device, where the source terminal S corresponds to the free end of Rf. As in an STM, the operation of NEMT is based on the control of a tunneling current across a subnanometer air or vacuum gap. The input and output resistances of NEMT are practically infinite, favoring its use as a transconductance amplifier. NEMTs can be integrated with NEMS transducer processes and can be utilized for analog processing of the sensor signals and driving the actuators, paving the path for all-NEMS systems. We are currently working on understanding the dynamics (time-dependent behavior) of the NEMT as well as demonstrating the NEMT operations using the lateral relays with both external resistors and integrated polysilicon resistors.
