The objective of this research is to develop energy-efficient programmable signal processing accelerators for heterogeneous multi-core mobile multimedia communication processors utilizing three-dimensional (3D) integration technology. The approach is to use the massive storage capacity and extremely high logic-memory data bandwidth enabled by 3D logic-memory integration, realized by vertically stacking high-performance logic die and high-density memory dies together, to fully exploit the parallelism inherent in most signal processing functions.
The intellectual merit lies in the research theme of jointly considering signal processing algorithm, programmable accelerator architecture, and memory modeling and optimization to most effectively exploit the unique features, i.e., storage capacity and bandwidth, provided by 3D logic-memory integration. Within the proposed scope, this research addresses video coding and forward error correction coding systems, which dominate the energy consumption of mobile multimedia communication signal processing. Because of the high storage density of dynamic random access memory (DRAM), this research will focus on 3D logic-DRAM integration and develop accurate 3D DRAM modeling and performance prediction capability in a truly technology-aware manner.
The broader impacts of the research include the potential to greatly improve the energy efficiency of future mobile multimedia communication devices by providing energy-efficient programmable signal processing accelerator design solutions. In addition, the research represents a first step towards establishing a new area of 3D very large-scale integration (VLSI) signal processing that naturally expands the traditional VLSI signal processing area. The project also promotes the education of a wide spectrum of students in advances in future nanoscale integrated circuits and 3D integration.
The objective of this sponsored research project is to develop energy-efficient programmable signal processing accelerators for heterogeneous multi-core mobile multimedia communication processors utilizing new three-dimensional (3D) integration technology. A variety of design techniques have been developed to address various fundamental challenges in the realization of 3D-based multi-core processors and their application in multimedia communication devices. The major research accomplishments include (1) Development of coarse-grained 3D dynamic random access memory (DRAM) architecture design solutions that can fully exploit the 3D integration technology; (2) Development of techniques for efficient implementation of decoupling capacitors in 3D processor-DRAM integrated systems that can effectively reduce the power supply noise in 3D integrated processors; (3) Development of design techniques that can greatly improve the processor die power delivery quality in 3D processor-DRAM integrated systems and meanwhile have minimal impact on DRAM storage capacity; (4) Development of application-specific accelerator design for low power video encoding in 3D processor-DRAM integrated systems, which can fully leverage the unique advantages of 3D integration technology to reduce image data access energy consumption in video encoding; (5) Development of design techniques for energy-efficient implementation of video encoding on reconfigurable embedded accelerator in 3D processor-DRAM integrated systems; (6) Development of techniques to use 3D integration to improve embedded digital signal processor (DS) computing engine in 3D processor-DRAM integrated systems; (7) Development of energy-efficient soft-error resilient cache memory design techniques for 3D processor-memory integrated systems.
