The objective of this project is to develop new test techniques that target small-delay defects in nanoscale integrated circuits. The approach is based on the use of the output-deviations measure as a surrogate "long-path" coverage metric for small-delay defects. The project will be carried out in partnership with AMD Corporation and other industrial collaborators.
Intellectual Merit: Small-delay defects, induced by process variations, crosstalk, power-supply noise, and resistive opens/shorts, etc., are major quality and reliability concerns in the semiconductor industry. Current industry practices are not only inadequate for small-delay defects, but test costs are skyrocketing as well (estimated to be more than 50% of manufacturing cost). This project is focused on test generation using scalable methods that can provide comprehensive defect screening for industrial circuits. It includes the following components: (i) a gate-delay-defect probability measure to model delay faults; (ii) use of gate-delay-defect probabilities for computing output deviations; (iii) layout-aware, deviation-based test-pattern selection/generation for high defect coverage.
Broader Impacts: This project will lead to higher shipped-product quality, increased in-field reliability, and reduced test cost. Benefits for society include reliable electronics for healthcare, cheaper and dependable computing platforms for servers, weather forecasting, financial transactions, and more, and realization of the much sought-after zero-defects for automotive applications. Students will be trained for the workforce through research experience, coursework, and relevant industry internships. A concerted effort will be made to involve under-represented groups, for example through the Semiconductor Research Corporation fellowship programs. Tutorials will be presented and special sessions will be organized at major conferences.
