"This award is funded under the American Recovery and Reinvestment Act of 2009 (Public Law 111-5)."
The objective of this research is to design and fabricate high performance nanowire field effect transistors with steep subthreshold slopes and large on-off ratios at low operation voltage, and integrate them for large-scale logic and stand-alone memory applications. The approach is to introduce gate-channel-source coupling in nanowire field effect transistors to achieve steep subthreshold slopes much sharper than the thermodynamic limit of conventional field effect transistors, and develop fast and reliable FLASH-like nanowire non-volatile memory for future, more portable electronics.
Intellectual Merit: the proposed research will exploit the inherent advantages of the Schottky-barrier nanowire field effect transistor structure, with the potential to have transformational impact on logic and memory cell design which will remain compatible with semiconductor chip technologies. These new devices will be characterized by much better gate control, faster operation and lower leakage power dissipation at reduced area and cost. Furthermore, very demanding device physics will be carried out to establish the most appropriate structures and operation conditions.
Broader Impact: the approach is expected to have substantial broader impact in the quest for new nanoelectronic devices, as it will introduce device structures with operational principles different from conventional devices, while at the same time benefiting from the vast experience with silicon technology. These devices will make urgently needed contributions to semiconductor industry in logic and memory technology. New nano-fabrication technology and nanoelectronic metrology will also be developed during the course of this research. As always, science and engineering education is the main interest and focus of this project.
