The objective of this research is to develop a new class of on-chip power electronics circuits that will enable highly granular, active power management for future multicore processors, allowing energy-delay trade-offs to be performed in the presence of workload variability. The approach is based on the introduction of magnetic materials as a "post-process" on a standard CMOS run.
Intellectual Merit. Current implementations employ off-chip, board-level voltage regulation and bring in independent supply voltages from off-chip. Such approaches are not scalable and require that power be delivered to the chip at highly scaled voltage levels, leading to unsustainable current demands. We specifically address how passive magnetic devices can dramatically improve the design of on-chip power management and delivery circuits by providing for high density energy storage on-chip. We will innovate new magnetic devices (inductors and GMR sensors) that can be implemented on a conventional CMOS process.
Broader Impacts. This project will allow the PIs to train graduate and undergraduate students in a truly cross-disciplinary research environment combining physics, nanoscale materials, circuit design, and power electronics applications. This research effort will also feed a new course at Columbia on power electronics, with a special emphasis on integrated approaches, bridging the disconnect between the power electronics community and the traditional integrated circuit design community. Significant effort will be made for K-12 outreach by systematically training highly motivated high school students within the program and also enhancing the interaction with the local K-12 educators.
In this project, we have developed a process for integrating high-performance thin-film magnetic inductors into conventional complementary metal-oxide-semiconductor (CMOS) processes and developed integrated dc-dc converters based on these inductors. These developments have allowed us to significantly scale the size of dc-dc converters, allowing them to be monolithically integrated with the designs they are powering. The power inductors provide high-capacity energy storege devices, which are generally not available in traditional semiconductor processes. This technology enables fine-grained power management (spatially and temporally) by providing dynamic scaling of the supply voltage in concert with the clock frequency to throttle power consumption at periods of low computational demand. The technology developed here has been spurn off as a start-up venture, led by the lead Ph. D. student working on the project. This company has already secured private venture funding and has a joint manufacturing agreement in place with TSMC, the world's largest semiconductor foundry. The concepts and designs developed from this work will enable significant improvements in performance-per-watt of future microprocessors in servers, desktops, and mobile devices. The approaches developed here should allow energy eficiency gain as high as 30% in processors for all computing platforms, resulting in a direct annual energy savings of almost 15 billion kWh nationally, and 50 billion kWh globally.
