This award is funded under the American Recovery and Reinvestment Act of 2009 (Public Law 111-5).
The objective of this research is to address the computational challenges in multi-core power distribution design by leveraging recent advances in single-instruction multiple-data (SIMD) graphics processing units (GPUs). The approach is to develop a massively parallel GPU-accelerated design engine to facilitate the analysis, design and verification of power-gated multi-core on-chip power delivery networks encompassing both electrical and thermal integrity issues.
Intellectual Merit: Aggressive fine-grained power gating is essential to pushing the performance vs. power envelope of current and future multi-core chip designs. This need introduces significant challenges in the design and verification of power delivery networks under complex power gating scenarios. While the recent GPU advances provide a potentially promising computing solution, the effective use of such SIMD compute power requires rethinking computed-aided design. In this work, GPU-specific computing paradigms, algorithms and implementations will be developed to address multi-core power distribution design and associated full-chip thermal challenges via efficient parallel computing on low-cost SIMD graphics processors.
Broader Impacts: This work exploits recent SIMD GPU based massively parallel platforms for addressing CAD challenges. The acquired experience is likely to contribute to computing advances in other science and engineering fields. The PI will promote the research participation from undergraduate students and students from underrepresented groups. The outcomes of this work will be integrated into the PI's graduate-level VLSI courses to provide educational and research experiences to students. The developed algorithms and methodologies will be disseminated in the research community at large and major semiconductor and EDA companies for potential industrial application.
