This award is funded under the American Recovery and Reinvestment Act of 2009 (Public Law 111-5).
The objective of this research is to develop and implement scalable bilinear algorithms for convolutions and transforms over the real field and finite fields. The approach is to first obtain bilinear algorithms by identifying cyclic structures and combining relevant cyclic convolution algorithms algebraically, and then reduce their additive complexities significantly.
The intellectual merit of this project lies in scalable bilinear algorithms for convolutions and transforms, which are suitable for efficient hardware implementations, and a novel common sub-expression elimination algorithm that greatly reduces the additive complexities of a wide range of bilinear algorithms. The research is organized under four themes: (1) scalable bilinear algorithms for convolutions and transforms over the real field; (2) scalable bilinear algorithms for convolutions and discrete Fourier transform over finite fields; (3) reduction of additive complexities; and (4) hardware implementation under the algorithm/architecture co-design methodology.
With respect to broader impacts, scalable bilinear algorithms have significant potential for impact on a wide range of applications, such as signal processing, telecommunications, and multimedia systems. The project integrates research with education and outreach activities to educate a wide spectrum of students in the interdisciplinary area of very large-scale integrated (VLSI) signal processing, which links integrated circuit hardware design with signal processing. The project also provides research opportunities and hands-on system design experience to graduate and undergraduate students and motivates local high school students to pursue higher education in science and engineering.
