Parallel computing in the form of chip multiprocessors has become an industry standard. The number of cores on a chip is expected to continue to increase in an effort to achieve continued performance growth while meeting thermal and power limits. However, the increasing power-performance scalability of multi-cores raises two main concerns. First, it is unclear how software will take advantage of the increasing hardware parallelism, and second, power consumption and thermal constraints are still a major design limitation.
Intellectual Merit This proposal focuses on a particular existing easy-to-program and easy-to-teach multi-core architecture, which provides a different approach to parallel programming, thus targeting the first concern above. The work intends to demonstrate the programmability of this architecture by incorporating it into parallel programming education at the college level. To address the second concern, the work aims to study the power consumption of this architecture and introduce novel power and thermal enhancements. Today?s microprocessor industry focuses on a single model for general-purpose multiprocessor computers. This proposal addresses the energy-efficiency of a new approach to parallel computing, which targets single task completion time. Ensuring that the new architecture meets power and thermal constraints will enable it to serve as a viable alternative approach to parallel computing.
Broader Impacts The broader impact of this work is its potential to expose students to multicore architectures and parallel computing. This includes providing undergraduate students with research experience in energy-aware computer architecture and parallel programming, as well as incorporating these topics into existing courses and introducing new courses. A main goal of the proposed activities is to attract young people to engineering, as well as broaden participation of students in varied scientific areas, including students from currently underrepresented groups.
