This award is funded under the American Recovery and Reinvestment Act of 2009 (Public Law 111-5).
The objective of this research is to utilize nanoscale transistors beyond the CMOS scaling roadmap for low power, high accuracy implementation of neural-inspired (neuromorphic) computing modules. These novel devices include feedback FETs, impact ionization MOSFETs, tunneling devices and ferroelectric transistors. The approach to achieve this technology is to use a complex electrical model of a neural computing cell, and map its behavior to a low hardware complexity circuit using future nanoscale transistor models. Known problems associated with these novel devices such as hysteresis behavior and inherent nonlinearity will be investigated as a beneficial property for fundamental analog neural building blocks, such as perceptron, achieving lower power and higher density.
This project will be the first application and investigation of nanoscale devices to self-learning neuromorphic computing platforms, enabling a very low power operation. In this seed project, as an application platform traditional VLSI and signal processing functions will be mapped to neuromorphic computing platforms. These functions include receive channel equalizers and branch prediction logic in RISC computers.
Integrated circuit design, characterization and modeling, with a deep understanding of future nanoscale devices for VLSI technology is a critical and growing need for the semiconductor industry. There is a growing need to move beyond traditional logic design for signal processing and computing platforms. The experience of using future nanoscale devices for various neuromorphic circuit blocks will be incorporated to graduate level circuits and device modeling classes, with strong emphasis on training future scientists and engineers with creative problem-solving skills in overcoming limitations of future nanoscale devices.
