The objective of this research is to design new cognitive power management techniques for memory dominated mobile devices that exploit the variable nature of the wireless channel. The approach is based on redefining the run-time architectural error tolerance of memory blocks according to the time varying tolerance of the application to hardware induced errors. This allows the margin of acceptable performance to be dynamically managed by the needs of the application utilizing the hardware unit at that instant in time.
The intellectual merit of the work lies in enabling designers to abstract the concepts of power efficiency and error awareness for memory dominated devices early in the design cycle, with significant implications on the cost, performance and reliability attributes of the overall structure.
The multidisciplinary nature of the project, which spans theoretical, circuit, system and experimental work, creates an exciting framework to engage students, educators and the community. The proposed research and education plan places an emphasis on expanding the engagement of the investigator in programs designed to attract undergraduates (particularly female students) and minority students from underrepresented groups into engineering. Finally, since power conscious mobile devices are rapidly becoming ubiquitous in every aspect of modern day society spanning government, corporate and private life, this work has particular significance in accelerating the rapid deployment of inexpensive and energy-efficient devices.
