The objective of this research is to develop a signaling scheme that produces near zero simultaneous switching noise for I/O circuits switching in a package or printed circuit board. In present packages and printed circuit boards, this is caused by the cavity resonances produced between the power and ground planes due to return path discontinuities. The approach is to replace the power planes using transmission lines that are matched at the source, thereby leading to un-interrupted current return paths. This approach can be applied to both 2D and 3D integrated systems.
Intellectual Merit: Today's electronic systems use a low impedance power distribution network. Contrary to this practice, high impedance transmission lines can be used to supply power, thereby eliminating the need for hundreds of capacitors. Using the proposed interconnection topology, it is expected that copper wires in the package would be sufficient to achieve a bandwidth of 1.6TBps or better between multi-core processors and memory.
Broader Impacts: The high-risk, far-reaching approach investigated in this program is beyond the current focus of the electronics industry, and thus lends itself to university-based research and development. The findings from this research and the approaches developed will be integrated into graduate and undergraduate courses. K-12 students and high school teachers are expected to participate in research, which provides engineering exposure and stimulates engineering interest.
With transistor scaling, a major bottleneck is power supply noise. Due to the noisy package environment, power supply noise can limit the communication speed between integrated circuit (IC) chips. The focus of thsi project was to investigate and develop new off chip signaling schemes that minimize power supply noise and other discontinuity effects. With the electronics industry moving towards 3D stacking of ICs and packages, one goal was to demonstrate these methods for such 3D integrated systems. The metrics chosen for comparing the developed schemes were power usage, layer count and reduction in decoupling capacitors as compared to existing methods. All of the methods developed used two common approaches namely, 1) using power transmission lines to provide voltage and current to the ICs and 2) compensation and coding techniques. These concepts enabled significant reduction in noise (30%-40%), improvement in signal quality (30-40%) and provided opportunities for reducing layer count (which depends on application). Several chips, packages and boards were fabricated through this project to demonstrate the advantages and disadvantages of the methods developed. Probably the most noteworthy and satisfying accomplishment was the incorporation of these findings into a senior level course titled "Introduction to Electronic Systems Packaging" at Georgia Tech. In this course, the students working in groups of two, designed and implemented the off-chip signal schemes on printed circuit boards which were then measured by them to quantify the noise being generated and signal quality achieved.
