The objective of this research is to explore the growth mechanism and transport properties of a novel type of III-V semiconductor nanowires and establish it as a viable nanotechnology building block that is suitable for high performance metal-oxide field effect transistor devices in a scalable and integrable fashion. The approach is to grow nanowire transistor with precise alignment and tailored lateral doping profile through controlled metalorganic chemical vapor deposition on appropriate substrates, passivate by atomic layer deposited high-k dielectrics, and transfer-print to desired substrates for heterogeneous integration.
The intellectual merit of this research is to open up a new direction in III-V device possibilities using the self-aligned planar geometry; and fundamentally advance the understanding of 1D semiconductor epitaxial growth aspects from nucleation, propagation, to dopant incorporation and activation at the nanometer scale, as well as surface states and Fermi level pinning and unpinning effect on carrier transport properties at nano-scale dimensions.
The broader impact of this research is to accelerate the advancement of fundamental nano concepts into engineering solutions by making the bottom-up nanowire growth method compatible with the manufacturable planar processing technology; to attract and retain women engineers and reduce attrition rate at the master degree level through active mentoring and community building; and to cultivate environment for elementary school girls to defy negative stereotype and confidently stay on track for a career in science and engineering.
The objective of this research is to explore the growth mechanism and transport properties of a novel type of III-V semiconductor nanowires and establish it as a viable nanotechnology building block that is suitable for high performance metal-oxide field effect transistor devices in a scalable and integrable fashion. The approach is to grow nanowire transistors with precise alignment and tailored lateral doping profile through controlled metalorganic chemical vapor deposition on appropriate substrates, passivate by atomic layer deposited high-k dielectrics, and transfer-print to desired substrates for heterogeneous integration. The intellectual merit of this research is to open up a new direction in III-V device possibilities using the self-aligned planar geometry; and fundamentally advance the understanding of 1D semiconductor epitaxial growth aspects from nucleation, propagation, to dopant incorporation and activation at the nanometer scale, as well as surface states and Fermi level pinning and unpinning effect on carrier transport properties at nano-scale dimensions. The broader impact of this research is to accelerate the advancement of fundamental nano concepts into engineering solutions by making the bottom-up nanowire growth method compatible with the manufacturable planar processing technology; to retain women engineers and reduce attrition rate at the master degree level through active mentoring and community building; and to cultivate environment for elementary school girls to respect and confidently embrace a career in science and engineering at an early age. The major achievement is that we successfully demonstrated 20-80 channel length GAA InGaAs MOSFET with EOT down to 1.2nm and SS lowest of 63 mV/dec. The student supported by NSF and SRC presented two IEDM papers as the first authors. The work gains wide interests in the device community and was reported by several media. All the results from this NSF project are published in 14 journal papers in the public domain including highly competitive conferences such as IEDM and IEEE EDL and Nano Letters.
