The objective of this research is to explore the growth mechanism and transport properties of a novel type of III-V semiconductor nanowires and establish it as a viable nanotechnology building block that is suitable for high performance metal-oxide field effect transistor devices in a scalable and integrable fashion. The approach is to grow nanowire transistor with precise alignment and tailored lateral doping profile through controlled metalorganic chemical vapor deposition on appropriate substrates, passivate by atomic layer deposited high-k dielectrics, and transfer-print to desired substrates for heterogeneous integration.
The intellectual merit of this research is to open up a new direction in III-V device possibilities using the self-aligned planar geometry; and fundamentally advance the understanding of 1D semiconductor epitaxial growth aspects from nucleation, propagation, to dopant incorporation and activation at the nanometer scale, as well as surface states and Fermi level pinning and unpinning effect on carrier transport properties at nano-scale dimensions.
The broader impact of this research is to accelerate the advancement of fundamental nano concepts into engineering solutions by making the bottom-up nanowire growth method compatible with the manufacturable planar processing technology; to attract and retain women engineers and reduce attrition rate at the master degree level through active mentoring and community building; and to cultivate environment for elementary school girls to defy negative stereotype and confidently stay on track for a career in science and engineering.
Nanoelectronic devices utilizing three-dimensional (3D) self-assembled nanowires (NWs) have unique nanoscale geometry which promise to reduce short channel effect (SCE) while offering high performance, low-power and monolithic integration of digital and RF devices. III-V NWs, owing to their high carrier mobility, are very promising as long as large arrays can be fabricated to increase total current output and reduce leakage. Generally, vertical array-based III-V NW transistors have been the focus because of the preferred NW growth direction by the vapor-liquid-solid (VLS) method; however, defect-free NW structures without massive stacking faults are challenging to grow and the out-of-plane geometry prevents high-speed operation because of the severe inherent parasitic capacitance. Making arrays of III-V NWs in-plane with the substrate is much more compatible for planar-process fabrication and defect-free structures ensure better performance. Previous work in the literature on RF performance, for planar NW transistor layout, is reported only from randomly spun-on or ex situ aligned or regrown III-V NWs. The major outcomes of research supported by this grant include excellent DC and RF performances achieved from site-controlled planar GaAs NW array-based high electron mobility transistors (HEMTs), using a unique VLS in-plane defect-free NW growth method discovered by our group. A patent that encompasses this discovery, "Method of fabricating a planar semiconductor nanowire" was awarded in August of 2014 (US 8,810,009). Using the planar NW platform, many kinds of transistors including MESFETs, MOSFETs, and HEMTs, as well as circuits have been demonstrated. In particular, the balanced DC/RF performance, for a gate length of 150 nm, fT and fmax ~ 33/75 GHz, sets the record among bottom-up grown array based nanoscale devices, including VLS nanowires, carbon nanotubes, or 2D sheets aligned in-plane with substrates. Furthermore, by continued down-scaling of the gate length and barrier thickness, plus changing the channel material to those with much higher mobility (such as InAs), the frequency performance should readily be improved. The intellectual merit lies in the realistic potential our demonstrated has validated of bottom-up grown nanowires for beyond Si CMOS logic and future III-V RF electronics. Broadly speaking, this work is redefining the public perception of bottom-up grown nanowires and accelerating nanoscience concept to real-world applications not only in high performance electronics, but in sensing, photonics, etc. In terms of education and training, students have been provided opportunities in a vertically-integrated and laterally-collaborative interdisciplinary research environment from simulation, state of the art crystal growth, device design, fabrication, to characterization. The broader impact of the funded project has been realized through dissemination of the research outcome via the 20+ journal publications, numerous conference presentations and invited seminars. In addition, outreach to the general public has been carried out through forums including the "Saturday Engineering for Everyone", engineering open house, research experience for teachers (RET) and research experience for undergraduate programs.
