The objective of this research is to develop a digital phase-locked loop (DPLL) that achieves low phase noise while being fundamentally robust to interferers and the effects of transport delays. The approach is to employ sophisticated digital control schemes so that the effects of circuit noise, external interferers, and loop latency can be explicitly modeled and accounted for in the digital feedback loop. This approach contrasts with existing loop filters, whose bandwidth is generally the only design parameter that can be modified to mitigate the effects of interferers or other undesirable non-idealities.
Intellectual Merit: In the approach pursued in this project, the analog components of the DPLL are modeled as a noisy plant in state-space form. When viewed from this perspective, controlling the noisy plant to generate the desired frequency can be posed as a linear regulator problem, which is a classical problem of optimal linear control theory. The observer-controller loop filter developed in this project is broadly applicable to a wide range of existing systems that employ PLLs. Furthermore, the inherent robustness to interference of the proposed DPLL enables its use in many emerging systems such as in direct-conversion and out-phasing transmitter architectures.
Broader Impacts: The research is integrated with an education program to help train both graduate and undergraduate students. The multi-disciplinary nature of the research will broaden the students' technical understanding, which will be indispensable for the next generation of engineers. The educational program also includes plans to improve the participation of undergraduate students and members of underrepresented groups.
Phase-locked-loop (PLL) is widely used in many electronic systems. In RF communication transceivers, for example, PLL is used to generate the desired RF frequency based on a reference crystal frequency, which typically operates at a much lower frequency (e.g., 26 MHz). A PLL is also used to distribute clock timing pulses in digital logic designs such as in microprocessors and for clock recovery in chip-to-chip interconnects. Although used in many different applications, the basic operation of the PLL is the same. The frequency of a locally controlled oscillator is adjusted to phase lock to a reference signal. Digital phase-locked-loop (DPLL) has been recently developed to exploit the increasing transistor speed of modern process technology. The salient features of the DPLL are that the phase detector is performed digitally using a time-to-digital converter (TDC), and the voltage-controlled oscillator (VCO) is digitally controlled and referred to as digitally-controlled oscillator (DCO). The use of TDC and DCO enable the loop filter to be fully digital. The all-digital nature of the loop filter provides the DPLL with many implementation advantages, among which are improved noise immunity from circuit non-idealities (e.g., charge pump feed-through, mismatches, etc.), compatibility with digital deep-submicron CMOS process, simplified testing and calibration, and ease of integration with digital baseband circuitries. The loop filter in existing DPLL is obtained by converting the continuous-time response of an analog PLL to a discrete-time approximation. As the loop filter is all-digital, more sophisticated control schemes can be used instead. In the proposed loop filter, the DCO and TDC are modeled as a noisy plant in state-space form. When viewed from this perspective, controlling the noisy plant to generate the desired frequency can be posed as a linear regulator problem, which is a classical problem of optimal linear control theory. As the optimal control is a linear feedback of the state vectors, which cannot be observed directly, a Kalman filter is used to estimate the state variables. The primary advantage of the proposed observer-controller DPLL is that it provides additional degrees of freedom necessary to mitigate the effects of circuit noise, external interferers, and implementation constraints such as digital transport delay. Such degrees of freedom are not available in existing loop filters, whose loop bandwidth is basically the only design parameter. The proposed observer-controller loop filter explicitly incorporates these constraints in a state-space formulation to provide the requisite degrees of freedom. Much of our work has focused on developing a clear fundamental understanding and addressing the many practical issues of an observer-controller DPLL.
