International Mini-Woorkshop series on An Assessment of Options for Post-CMOS Emerging devices and Related materials
The objective of this proposal is to request funds for travel of about 20 faculty members to the International Mini-Workshop series on An Assessment of Options for Post-CMOS Emerging devices and Related materials. that will be held in 2010. The workshops will be held in Braza, Italy-April 2010, San Francisco, CA July 2010, and Seville, Spain September 2010. These meetings are held adjacent to international conference so that other attendees with the background in Emerging Research Devices (ERD) and Emerging Research Materials (ERM) can participate in the meetings. The University faculty invited to attend these meetings contribute valuable input to the four mini-workshops. This set of mini-workshops is in continuation of the series of workshops that have been held in 2004, 2006 and 2008
Intellectual merit:
These mini-workshops provide highly interactive forums where key research leaders in the Semiconductor Industry and the related academic communities seek to evaluate the status of nanoelectronics research, discuss potential applications, and define promising future research directions. This will enable the 2011 version of the International Technology Roadmap for Semiconductors (ITRS) to reflect an informed view on key scientific and technical challenges related to post-CMOS information processing technologies proposed for post-CMOS devices, based on new quantitative analyses and projections.
Broader Impact: The educational value and planning impact of these workshops on the international research community are quite substantial. Several universities (e.g., Stanford, U. Minnesota, U. Tokyo, ) use the ITRS chapters on Emerging Research Devices and Emerging Research Materials resulting from these workshops as texts in their Nanoelectronics courses. Also several international research funding agencies (e.g., the SRC, NSF, and NIST Nanoelectronics Research Initiative, the EU Framework Program 8, ) use the material in these chapters as inputs to their decisions on research directions in their Nanoelectronics research programs.
Electronic semiconductor devices are the underlying backbone for a huge and growing number of products and services we use daily, including cell phones, PCs, digital cameras, solid-state lighting, TVs, cable communications, the internet, medical devices, automobiles, etc. The emergence and spectacular growth of these revolutionary applications over the past 40+ years has been enabled by the physical shrinking of the fundamental device (the transistor) by 2x every two – three years, resulting in a cost reduction per transistor of 35%/year. (A microprocessor chip may contain over two billion transistors.) This whopping scaling of transistors and integrated circuits (invented and first developed in the U.S.), has rapidly increased the capacity and speed of semiconductor chips. This is enabling tremendous growth in productivity across all components of our economy, and thereby adding sorely needed jobs within the U.S. For example, the worldwide semiconductor market in 2011 is projected to exceed $315B of which the U.S. share is roughly $150B (48%). This supports 200,000 jobs in the U.S.-based direct manufacturing industry and an additional 100,000 jobs in companies that are suppliers to the semiconductor industry. At the projected growth of the semiconductor market of 5+% for 2011, the economy will add approximately 20,000 jobs in the semiconductor and supplier industries and another 20,000 in related service industries. For very fundamental reasons, this shrinking or scaling of the transistor may slow down and end by 2026. Continued growth of the semiconductor industry, and its major impact on the U.S. economy, therefore will require discovery and development of revolutionary new technologies at the nano- or atomic-scale exploiting new physical phenomena. To this end, the mini-workshops reported herein examine, discuss, critique, and encourage (when appropriate), new ideas and technological approaches for continuing this revolutionary atomic-level scaling of information processing devices and its benefits for several decades beyond 2026. This report discusses eight promising research memory chip technologies any one of which may have an important impact on many electronic products. For example, integration of a viable, non-volatile memory technology on a microprocessor chip in place of the volatile SRAM cache memory may dramatically reduce the time currently needed to boot or re-boot a PC. This same technology may increase the capacity of a Thumb Drive to over 128 Gbits. Also discussed are five new approaches for performing information processing functions to supplement and, eventually, to replace the current CMOS integrated circuit technology. Each of these new approaches uses a new physical phenomenon as a "token" or "computational variable" to perform information processing, but each faces difficult challenges that must be overcome to demonstrate feasibility. This report examines each new approach proposed for memory and for information processing to determine its potential performance and its major technological barriers that must be overcome to attain its potential.
