The objective of this research is to introduce new power delivery schemes in Systems-on-Chip that achieve higher power efficiency. The proposed approach is to replace the numerous linear regulators within the system with more efficient fully-integrated switching alternatives. The large size and cost associated with switching regulators is addressed by switching at 300MHz-600MHz, which reduces the required passive components to where they can be integrated on-chip and on-package-substrate.
The intellectual merit of this research is to leverage the ultra-high speed-to-power ratio of sub-65nm CMOS technologies to enable integrated switching regulators to operate above 300MHz while maintaining power conversion efficiency that is better than linear regulators. The silicon area overhead of on-chip passives are handled through stuffing the regulator?s power switches, input and output capacitors, and control circuitry directly underneath the inductor. The magnetically-induced losses are reduced by strategically placing the stuffed circuits based on how they are configured in a switching regulator topology.
The broader impact of this research is that it improves power efficiency while preserving small footprint and cost. This makes many devices that are currently limited by unrealistic size or battery life requirements, such as biomedical implants, technically and economically feasible. The PI will complement this research activity with education by developing curriculum that provides the missing link between traditional power electronics education and state-of-the-art Integrated Circuits. Additionally, the PI will provide graduate and undergraduate students, including those from underrepresented groups, with the opportunity to interact with industry and acquire necessary skills for a successful engineering career.
