This grant is funded jointly by the Electronics, Photonics, and Magnetic Devices (EPMD) Program in the Division of Electrical, Communications and Cyber Systems (ECCS) and by the Electronic and Photonic Materials (EPM) Program in the Division of Materials Research (DMR).
Miniaturization lies in the heart of technological advancement in the semiconductor industry. However, a substantial change in the design of the basic building block which is the metal oxide semiconductor field effect transistor (MOSFET) is required as the current architecture and materials are reaching limits imposed by the laws of physics. A solution to this conundrum is the use of new materials such as two dimensional (2D) atomic crystals that we have only recently begun to investigate in detail. Such materials are the ultimate small medium allowing the fabrication of high quality devices. The goal of this work is to exploit and further our understanding of the properties of these nanostructured materials and to introduce device structures with operational principles different than the conventional technology, while at the same time continuing to benefit from the already existing vast experience with silicon technology. This work responds to the widely recognized need for progress in nanoelectronics and technology as the current paradigm is reaching the fundamental physical and economic limit. The outcomes of this work also include new nano-fabrication technology and nanoelectronic metrology which will add to the national nanotechnology portfolio, a vital component for the future technological dominance of the USA. Technologies cannot be advanced or applied in the absence of highly qualified scientists and engineers. Two graduate students, one from UMBC and one George Mason University will gain their Ph.D. while interacting very closely with each other and our collaborators at NIST, preparing them for careers in industry, academia and government. Many undergraduate students will also be benefit, for example by doing their senior design projects. Parts of the research will be integrated into graduate level courses currently taught by both PIs and results will be presented in seminars, conferences and peer reviewed publications.
The goal of this proposal is to produce new knowledge in the area of surface preparation methods so as to enable atomic layer deposition of high-quality dielectrics on two-dimensional (2D) atomic crystals MOSFET applications. The 2D materials, such as the isolated monolayer and few-layers of MoS2 and WSe2 will be grown at wafer scale for both in-situ characterization and circuit integration. Their surface will be carefully engineered with self-assembled monolayers of molecules to enable the formation of high-quality interface during the atomic layer deposition of dielectrics. The surface preparation results will be analyzed in-situ during the deposition of dielectrics, and compared with physisorbed dielectrics. This surface modification will enable high-performance 2D atomic crystal MOSFETs and circuits which will nevertheless remain compatible with silicon technology. These new devices will be characterized by better gate control, faster operation and lower leakage power dissipation at reduced area and cost. The acquired surface preparation technology will enable integration of 2D MOSFETs and electronic circuits, and act as platforms to demonstrate the properties of materials and interfaces. This work will exploit the inherent advantages of the 2D nanomaterials and devices, with the potential to have transformational impact on the next generation of devices and electronic circuits.
