Analog-to-digital converters (ADCs) are required whenever a signal from the physical world must be translated into a form that can be understood by a microprocessor or computer. Example applications include implanted biomedical devices for assistive technology, autonomously powered sensors for untethered health care monitoring, accelerometers and other sensors used in smartphones, and chemical sensors used in automotive and security applications. In most of these systems, available energy is severely constrained by battery power or scavenged energy limits. An additional difficulty for high precision ADCs is the requirement for calibration, which increases both manufacturing and operating costs. The goal of this work is to leverage advancement in digital integrated circuit manufacturing technology to provide a class of energy-efficient self-calibrating ADCs applicable across a wide range of rapidly growing technology areas. The proposed energy efficient approach would reduce ADC power consumption by at least a factor of 10, enabling new system architectures and capabilities, as well as extended battery life in existing systems. Self calibration allows reduction in manufacturing and operating expense, critical to providing the cost improvement end users expect.
In the proposed work, prototype integrated circuits will be designed, fabricated, and tested in a nanoscale (28nanometers) integrated circuit process. (The design and verification process will be carried out using state-of-the-art design software and test equipment available in the investigator's research lab. This in itself is a valuable workforce education experience, as the student researcher will be carrying out a design process very similar to that used in industry.) Scaling of integrated circuit technology to nanometer dimensions has enabled dramatic improvement in digital power efficiency, with lower power supply voltage and decreased power consumption for logic functions. However, most traditionally prevalent ADC architectures are not well suited to the lower supply voltage environment, and investigation is ongoing for other architectures. The improvement in time resolution enabled by increased digital speeds naturally drives design toward time-domain architectures, which have shown promise but have not yet been able to provide both high accuracy and high energy efficiency. The proposed activity combines the principal investigator's previous work on precise time-based circuitry with digitally calibrated ADC techniques. The resulting research will enable a class of ultra-low-power, efficient ADC architectures suitable for a wide range of emerging applications requiring low cost, high accuracy, and energy efficiency.
