The demand for smaller, more efficient electronics has driven commercial companies to push the limits of scaling for transistors. Devices have moved from the 2D paradigm into the 3D paradigm for single transistors on the order of tens of nanometers. Highly miniaturized devices introduce reliability concerns such as hot carrier injection, where large undesirable currents lead to overall lifetime degradation and poor performance. Engineers often use simulation tools to understand hot carrier effects in devices. In order to reduce complexity and simulation time these tools abstract away much of the detailed physics which is necessary for the complex and miniaturized novel devices used today. This work will use a novel 3D simulation approach that is able to capture the necessary detailed physics for modeling the next- generation of devices. Understanding the physics of failure for these devices will ultimately lead to smaller, cheaper and more reliable electronics for the end user. This work also has the potential to impact our understanding of complimentary devices (e.g. LEDs, Solar Cells, etc.) and has implications for the renewable energy industry, resulting in increased access to affordable, reliable and clean energy to consumers around the world.
This work will use a Monte Carlo code suite with full-band capabilities to perform the first of its kind 3D model of hot carrier injection in gate-all-around field effect transistors. Anduril could prove to be the next gold standard of device simulation tools for modern 3D mianiaturized technologies. 3D simulations of hot carrier injection in stacked gate-all-around transistors will be compare to experimental characterization proposed in this work. The PI has access to vertically stacked gate-all-around transistors from imec which have been shown to have near-ideal subthreshold slopes (~67 mV/dec). With the PI?s secondary appointment she has the ability to recruit graduate talent and access to a full suite of reliability testing equipment in the Radiation and Reliability group at Vanderbilt. DC stress conditions and 1/f noise measurements will be conducted under the advisement of the PI at Vanderbilt. Additionally, simulations using the Anduril code suite will be conducted using the ACCRE super- computing cluster. Simulations will occur in phases beginning with a single gate-all-around transistor, whose reliability has been studied experimentally, and ultimately a stacked gate-all-around architecture, whose reliability is less understood. The work proposed by the PI is timely and relevant given the current trends moving to vertically stacked gate-all-around transistors, and the large knowledge gaps that still exist for understanding the physics of failure driving hot carrier degradation in these devices.
This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
