This award will support research aimed at the development of a scanning tunneling microscope on a silicon chip. It is the purpose of the research to demonstrate that the entire STM can be constructed with the microfabrication technology associated with the etching of silicon. A planar batch-microfabrication process will be used to produce an integrated STM scanner and tip on a silicon substrate using deposition patterning and etching techniques commonly used in the manufacture of integrated circuits. The device will have dimensions of 6 X 200 X 1000 microns, and it will include a thin film piezoelectric actuator for scanning the tip over the sample surface. If successful, this work could lead to a new and very inexpensive class of microscopes for the study of many phenomena on an atomic scale. It could also lead to a new class of extremely sensitive sensors for acceleration and force measurement.

Agency
National Science Foundation (NSF)
Institute
Division of Electrical, Communications and Cyber Systems (ECCS)
Application #
8917552
Program Officer
George A. Hazelrigg
Project Start
Project End
Budget Start
1990-06-01
Budget End
1994-03-31
Support Year
Fiscal Year
1989
Total Cost
$375,931
Indirect Cost
Name
Stanford University
Department
Type
DUNS #
City
Palo Alto
State
CA
Country
United States
Zip Code
94304