9404133 Kushner The Semiconductor Industry Association (SIA) has set the goal to achieve industry wide ).18um feature sizes in microelectronics devices by 2001 for wafer sizes as large as 40cm. These goals place extremely tight and tolerances on the uniformities of ion and radical fluxes to the surface are governed by the uniformity of their generation and the uniformity of potential gradients or flow fields which drive them to the substrate. These fluxes and gradients are highly sensitive to electrode topography which perturbs the plasma. Examples of electrode topography are the wafer itself, protruding clips from wafer holders bolt holes, and discontinuities in electrode materials on otherwise smooth surfaces. Plasma properties can even be influenced by metals or or dielectrics placed under the wafer. The researchers propose to perform a program of computer modeling to assess how electrode topography affects the uniformity of ion and radical fluxes to the substrate in plasma processing reactors, and propose methods to remediate or capitalize on those effects. In this effort we will build upon and further develop existing 2-dimensional hybird models of plasma etching and deposition reactors. The consequences of electrode topography on plasma properties will be assessed with regard to etching trench profiles, dust particle traps, and differential wafer charging.
