9810923 White This research and education program addresses the study of quantum charge transport and storage in ultra-thin, hetero-insulator, nanostructures for application in high density, low-power, low voltage, nonvolatile semiconductor memories (NVSM's), application specific integrated circuits (ASIC's) and low-voltage, low power, scaled CMOS circuits. Our studies focus on charge trapping in ultra-thin dielectrics with a combination of novel test structures and charge pumping experiments to determine the spatial and energetic trap distributions in the region near the Si-Si02 interface. Unique test structures and instrumentation are employed to examine the endurance of scaled novel SONOS nonvolatile memory nanostructures in their erase and write modes. In the case of ultra-thin dielectrics for scaled CMOS devices our research addresses stress-induced leakage currents (SILC) and trap-assisted tunneling. The PI's research employs advanced fabrication techniques, such as RTA oxidation of nitrogen implanted silicon, and analytical characterization techniques, such as AFM and angle-resolved XPS, to form and analyze the spatial and compositional structure of these ultra-thin dielectrics. The above research will lead to an understanding of charge trapping in ultra-thin dielectrics and advanced semiconductor devices while providing a strong educational program in scaled NVSM and CMOS devices. ***
