9871319 Martin Early 21st century opportunities for gigascale and terascale integration will be governed by a hierarchy of limits whose five levels can be codified as: 1) fundamental physics, 2) material specific properties, 3) device, 4) circuit and 5) system. At these levels of integration the most restrictive limits in this hierarchy will not be imposed by transistors performing computing functions but rather by interconnection networks performing communication functions. A key interconnection level of this hierarchy that will be severely challenged by gigascale integration is the chip-to-module interconnect that integrates the packaged chip (or circuit) into the system (e.g. onto a printed wiring board). The strategy for addressing this problem is to develop the new frontier of wafer level batch packaging (WLBP) technologies for chip-to-module interconnection, Wafer level batch packaging is envisioned as a process that creates the signal input/output (1/0) and external power contacts and encapsulates the finished silicon die prior to dicing the wafer. At its heart, WLBP will provide an interconnection framework for integrated circuits (ICs) so that before dicing the wafer each die has all the functions (e.g. external electrical contacts, encapsulation of the finished silicon) of a conventional, fully-packaged IC. Specifically, we propose that a scheme integrating a compliant interposer layer and flexible leads on the device side of the die be used to create a chip-scale package using massively parallel fabrication methods carried out entirely at the wafer-level: The purpose of this equipment request is to provide in one location the resources needed to conduct a majority of the steps required for developing wafer level batch packaging and the ability to fully characterize, test, and analyze all stages of the work on 125mm and 150mm wafers. It should be emphasized that this work must be conducted at these wafer sizes instead of on smaller wafers or pieces of wafer in order to fully ad dress WLBP issues, and to produce results that are widely useful to other leading edge workers in the semiconductor chip research and technology community. The result of this effort will be a set of enabling technologies (design and process) that will allow ICs to be fully packaged in wafer-form and ready for full testing, burn-in, and system assembly with no further packaging steps required. ***
