This Small Grant for Exploratory Research (SGER) supports simulation studies of a new architecture for parallel computation. The new architecture, mirror memory, is a variation on the snoopy cache coherence techniques that are possible in bus-based multiprocessors. A mirror memory system is a network of processor-memory pairs, interconnected by high-speed fiberoptic links. The processor-memory interface at each node of the network keeps track of shared variables that the node has copies of. Any time the processor writes a new value for one of these shared variables, the new value is multicast to all other nodes that have copies of the variable. This is "snooping in reverse". In a normal snoopy cache, the bus interface makes sure that its own processor has the correct data; in mirror memory, the interface makes sure that every other processor has the correct data. Trace simulations based on large-scale scientific programs are being used to establish the network and interface speeds required for transmitting new values, and to determine the effects of hot spots in large networks. Detailed simulations of network and interface operation determine the effects of proposed mechanisms on program running times.
