New device simulation and layout tools and a new device fabrication process are being developed for the Caltech freshman course in solid state devices and integrated circuits, a two-quarter sequence offered annually to approximately 90 majors and non-majors. The unusual goal of this class is to excite interest among freshman in solid state electronics in particular, and engineering in general. Hence the underlying curricular strategy is to appropriately simplify device physics to the level of intuition and simple mathematics, and to simplify the fabrication process as much as possible so as to make the first undergraduate laboratory experience very positive. To this end, design of a software toolbox for device simulation and layout enables freshmen to better understand device operation at an intuitive level and to avoid design mistakes in device and circuit layout. A new fabrication process centered around the use of spin-dopants will allow use of both n-type and p-type dopants with greater ease, reliability and safety. Device simulation and layout tools and the use of both dopant types will enable the present curriculum to be expanded to the design and fabrication of bipolar and CMOS devices while retaining the simplicity crucial for the process. This will be a significant advance in the teaching of undergraduate courses in the design and fabrication of microelectronic devices.
