Verification and logic simulation systems shall be developed within this undertaking and dedicated to projects involving VLSI design-for test. Individual projects include: * Diagnostic chip for IEEE Standard 1149.1 boundary-scan boards. * Self-test using MISR and parallel shift register sequence generator. * Burst-error correcting and self-repair ROM. * Test by approximation of Boolean function system.

Project Start
Project End
Budget Start
1993-03-01
Budget End
1995-11-30
Support Year
Fiscal Year
1992
Total Cost
$32,333
Indirect Cost
Name
Drexel University
Department
Type
DUNS #
City
Philadelphia
State
PA
Country
United States
Zip Code
19104