Wulf This project is building and measuring experimental memory systems that match the high data rates of processors with the low random access data rates of memory parts. The goal is to detect streams of memory references at compile time and use a smart memory controller to prefetch the streams at run time. The memory controller can use features of the memory system such as page mode, nibble mode, or Rambus to maximize the data rates of the memory parts. It then buffers the streams until the processor asks for the data. The project includes compiler research as well as research into the architecture of the memory controllers. This is similar to the vectorization efforts on such machines as the Cray supercomputers, but more general since a smart memory controller can be designed for any combination of processor speeds, memory features, and program characteristics.
